1. Field of the Invention
The present invention generally relates to a burst-mode clock and data recovery circuit using phase selecting technology.
2. Description of Related Art
With the growth of the wideband application, the need for the band width is raised. Optical fibers provide an extraordinary band width, good transmission quality and stability, which is a final solution for the wideband requirement. Currently, the most popular manner for achieving the scheme of optical fiber to home is through a low cost passive optical network (PON).
FIG. 1 is a schematic diagram illustrating a conventional passive optical network. Referring to FIG. 1, a passive optical network 100 comprises an optical line termination (OLT) 110, an optical distribution network (ODN) 120 and a plurality of optical network units (ONUs) 130. The optical line termination 110 is disposed at a head end and is able to be connected to an outside network for providing various network services such as internet, digital TV, high definition TV (HDTV) or voice over IP (VOIP). Those services are broadcasted to each of the optical network units 130 through the optical distribution network 120, such that users may pick up the desired service.
The optical distribution network 120 consists of an optical fiber and an optical splitter. The optical splitter is a passive element, which works without the need of power or maintenance. One end of the optical splitter is connected to the optical line termination 110 and the other end is connected to each of the optical network units 130. The optical splitter splits an optical signal sent by the optical line termination 110 into equal parts, distributes the same to each of the optical network units 130 connected therewith, and collects the signals uploaded by the optical network units 130 into the same optical fiber and transmits the same to the optical line termination 110. The optical network units 130 is usually disposed at a position close to a user end and classified into schemes such as fiber to the home (FTTH), fiber to the building (FTTB), or fiber to the curb (FTTC) according to different disposing position. Once a user intends to upload information such as a file transfer protocol (FTP) file or a video conference, the information can be uploaded through the optical network units 130.
Since the passive optical network adopts a point to multi-point structure, the uploaded data is collected in the same optical fiber by the optical splitter. Accordingly, the data to be uploaded by the optical network units 130 is transmitted through a time division multiplexing (TDM) manner based on IEEE 802.3ah and ITU G.983/G.984. The optical network units 130 can only upload data in a time slot arranged for the optical line termination 110, and the phases of data that the optical network units 130 upload to the optical line termination 110 are not all the same. Moreover, since the uploaded data of multiple user ends is uploaded through a time division multiplexing manner and each user may use a single optical fiber channel in its own time slot, the time for transmitting data by each user end can be reduced largely. Upon such circumstance, if the recovery process is executed by the conventional data recovery circuit, an effectiveness of bandwidth usage is wasted because the time for lock and recovery is too long and the time for the user to upload data is reduced in such structure. Accordingly, for the burst-mode data transmission process, a burst-mode receiver is required to be disposed in the optical line termination 110 to fast recover the clock and phase of the received data so as to use the bandwidth more effectively.
The conventional data recovery circuits with continuous mode can be classified into two types, in which the first type is a data recovery circuit based on a phase-locked loop. FIG. 2 is a schematic diagram of a conventional data recovery circuit based on a phase-locked loop. Referring to FIG. 2, a data recovery circuit 200 includes a phase frequency detector 210, a loop filter 220, and a voltage control oscillator (VCO) 230. The locking manner of the data recovery circuit 200 is to compare a phase and a frequency of a clock generated by the voltage control oscillator 230 with those of input data. When a difference of the phase and the frequency is occurred, a frequency of the voltage control oscillator 230 is changed by a control signal. When a difference of the phase and the frequency is not occurred, the data recovery circuit 200 reaches a stable locked state.
The second type is a data recovery circuit using double loops. FIG. 3 is a schematic diagram of a data recovery circuit using double loops. Referring to FIG. 3, a data recovery circuit 300 includes a phase frequency detector 310, a loop filter 320, a voltage control oscillator 330, a phase detector 340, a loop filter 350, and a voltage control delay line (VCDL) 360. The locking manner of the data recovery circuit 300 is to compare a phase and a frequency of a clock signal generated by an external reference clock and a voltage control oscillator 330 on an upper side with those of input data, so as to generate a stable output clock for the delay-locked loop on a downer side. When the data enters the data recovery circuit 300, the phase instead of the frequency thereof is compared with that of a clock signal with fixed frequency. When no phase difference is occurred, the data recovery circuit 300 reaches a stable locked state.
To create a data recovery circuit having characteristic of fast locking, a burst-mode clock of oversampling is required. The oversampling is to use clock signals with same frequency and different phase to sample the data, respectively. FIG. 4 is a schematic diagram illustrating a conventional three-times oversampling process. Referring to FIG. 4, three clock signals are used for sampling the data respectively, which is called three-times oversampling. For the data state sampled by the three clock signals, the states of each two of them are calculated through an XOR operation and which two adjacent clock signals that the data edge is positioned between are obtained after calculation and voting of a digital circuit.
For example, FIG. 5 is a schematic diagram illustrating a conventional phase selecting method. Referring to FIG. 5, the data edge is appeared between the clock signals #0 and #2, and therefore the clock signal #1 can be selected and used as the clock signal for data recovery. When performing phase selection, the oversampling phase selecting circuit may determine the sampling clock through the selection of the digital circuit, which is suitable for applications of fast locking. However, such a structure still lacks the capability for eliminating phase difference in the circuit. When a number of the data jitter is increased, the sampled phase may be incorrect so as to cause an error on data recovery.